1. Technical Field
Various aspects of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a semiconductor apparatus including a chip selection circuit.
2. Related Art
In an effort to increase an integration density of a semiconductor apparatus, a three-dimensional (3D) semiconductor apparatus that stacks and packages a plurality of chips into a single package is recently being developed. Since the 3D semiconductor apparatus includes multiple chips in a single device, the 3D semiconductor apparatus is configured such that an electrical signal can distinguish each of the plurality of chips from other chips and select a specific chip from the plurality of chips.
FIG. 1 is a diagram showing a configuration of semiconductor apparatus that comprises a related-art chip selection circuit. As shown in FIG. 1, three chips Chip1 Chip2 and Chip3 constituting the semiconductor apparatus are stacked one on top of another, but are not in exactly vertical alignment. Each of the chips Chip1 to Chip3 comprises separate chip selection pins (or pads) 1 and 2 to receive chip selection signals. Each of the chips Chip1 to Chip3 is applied with two voltages, e.g., an external voltage VDD and a ground voltage VSS through the two chip selection pins 1 and 2. Therefore, a specific chip can be selected from the three chips Chip1 to Chip3 based on the two voltages VDD and VSS applied. As shown in FIG. 1, since the related-art semiconductor apparatus includes the two chip selection pins 1 and 2, four chip selections are possible at the maximum.
However, since the related-art semiconductor apparatus is required to be equipped with separate chip selection pins as described, it is difficult to secure a surface area for the chip selection pins which strictly limits the number of available chip selections. In addition, since separate wire connections are needed to provide the voltages VDD and VSS to the chip selection pins, a complex wiring structure is necessary. Furthermore, according to the related art, since the chips are stacked in the vertically non-aligned pattern, a package structure is complicated and packaging the plurality of chips into the single package is difficult.